5 Write data. 3. Multiple Intellectual Property (IPs) are integrated in a single SoC and these IPs communicate with the help of various bus protocols. 6. Fully nonblocking with completely separate read and write paths; ID based transaction ordering protection logic; and per-port address decode, admission control, and. Short burst of or alternating read/write data. #- Configure the AXI3 Slave VIP interleaving depth >1. Abstract. By continuing to use our site, you consent to our cookies. No. AXI3 master . Write Data Interleaving in AXI. newest, i read "AMBA® AXI Protocol. I'm studying about AMBA 3. {"payload":{"allShortcutsEnabled":false,"fileTree":{"src":{"items":[{"name":"axi_atop_filter. Previous Section. UVM TestBench architecture. 一致性：所有接口子集都使用相同的传输协议。. Parameters axi_req_t: type. The problem I am facing is in AXI interface of MIG where 4-bit ID signal is present for all the transactiThis site uses cookies to store information on your computer. Where interleaving is supported, the WID and RID signals will indicate which of the interleaved transactions the data transfer relates to. By interleaving the two write data streams, the interconnect can improve system performance. Upload File; Most Popular; Art & Photos; Automotive; Business; Career; Home; Documents; AXI OverviewA multi-channel DDR interleaving control method and device, and a storage medium. In 2010, a new revision of AMBA, AMBA4, defined the AXI4, AXI4-Lite and AXI4-Stream protocol. #- Check that the Interconnect is forwarding the correct write data with respect to address issued. esign and. For Design specification and Verification plan, refer to Memory Model. 4 Write interleaving. AXI3 supports write interleaving. Linux is restricted to the lower half of DRAM (0x00000000 to 0x1ffffff). 16. >In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave? First of all, an AXI4 master must not issue interleaved write data. AXI is arguably the most popular of all AMBA interface interconnect. Typical Use Case for AXI DMA and AXI4 Ethernet. Tian Sheuan Chang Shared-link AXI provides decent communication performance and requires half the cost of its crossbar counterpart. when the WID is present in the old AXI version, a WDATA re-order mechanism will be inferred, and thanks to the remove of WID, we do not need that mechanism any longer. 8. AXI nonblocking crossbar interconnect with parametrizable data and address interface widths and master and slave interface counts. For example, we can access all four modules concurrently, obtaining parallelism. Thank you for your feedback. One major up-dation seen in AXI is that, it includes information on the use of default signaling and discusses the interoperability of components which can’t be. 1. Help me to understand the reasoning behind the following ordering rule imposed by AXI protocol for write data interleaving. Module axi_to_mem_interleaved. scala . 全面规范化：便于客户采用。. You cannot interleave transactions using the same ID, so the data transfer IDs are the link to the preceding address transfer IDs, telling the destination of the transfer which transaction they are for. p. 2. . Related content. Transaction ID信号，使AXI4协议可以完成自身的乱序机制，从AXI3到AXI4的进化中，write interleaving被取消了，大的方向下，AXI遵循着相同ID顺序执行，不同ID乱序执行的原则，同时从主设备-互联网络-从设备的连接中，Transaction ID可能会出现额外的位扩展. To avoid a deadlock situation, a slave interface must have a write interleaving depth greater than one only if it can continuously accept. #- Configure the AXI3 Slave VIP to interleaving depth of 1 #- Check that the Interconnect is forwarding the transactions to the AXI3 Slave VIP without write data interleaving. Thank you. A typical verification plan for AXI. The AXI protocol provides the dedicated channels for memory read and write operations. Open, closed, and transaction based pre-charge controller policy. When the AHB subsystem is bridged to an AXI subsystem through a combination of DW_ahb_eh2h and DW_axi_hmx, it is possible to do DMA transfers between AHB and AXI peripherals. Regarding write data interleaving, the requirements are different from those for read data. Commands are determined by the first two bits of those 34-bit words. Working of DMA Controller. Re-ordering implies the transactions complete in a different order to that the AR channel transfers were completed, whereas interleaving suggests that more that one read data stream can be active, so data in successive transfers could be for different transactions. m. LogiCORE IP AXI Interconnect v2. import all of my_pkg into your testbench. 2. The DMA controller registers have three registers as follows. Write buffer between stage 1 and 2 to store interleaving write packets Parameters of AXI4[-Stream] protocol can be adjusted in AXI4. 2. awaddr { Write address, the write address bus gives the address of the transaction. If the slave has a write data interleave depth of two, the slave can accept two addresses of interleaving data. here is the part axi slave rtl generated by vivado. Read now: data analyst course in hyderabad. View AXI Notes. 0 interconnect. 1A, the data transmitted by the AXI masters through an NoC router are transferred to an AXI slave 30 through an NI 20. The DMAC does not generate interleaved write data. recently, i read "AMBA® AXI Protocol. AXI Port. mapping the n word access ports to m interleaved banks. Write buffer between stage 1 and 2 to store interleaving write packets Parameters of AXI4[-Stream] protocol can be adjusted in AXI4. 2. Systems and methods consistent with the present invention relate to a Network-on-Chip (NoC) system employing the Advanced eXtensible Interface (AXI) protocol and an interleaving method thereof, and more particularly, to an NoC system employing the AXI protocol and an interleaving method thereof, capable of smoothly transmitting data according to the interleaving acceptance capability of an. A master interface's write interleaving capability is the number of active transactions for. out of order* 4. 0 axi interleaving - Architectures and Processors forum - Support forums - Arm Community - AMBA 4 AXI4-Stream Protocol SpecificationOutput (MI) SIZE = si. request regardless if the request was a write or a read. but i have two questions about AXI afterPrefix A Denotes global Advanced eXtensible Interface (AXI) signals: Prefix AR Denotes AXI read address channel signals. to request that BC PharmaCare make all long acting treatment options for the treatment of ADHD accessible) Paragraph 2 – ADHD (Optional). Intended audience This specification is written for hardware and softwa re engineers who want to become familiar with the Advanced Integrated Memory Controller . Everything runs fine, the Linux application can start the VDHL AXI master to. 1 Answer. AXI Interconnect v2. The out-of-order means a relationship between address PupilPath Login and data. AHB supports the locked transfer. >In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave? First of all, an AXI4 master must not issue interleaved write data. mem_rdata_i: input mem_data_t [NumBanks-1:0] Memory stream. The master can assert the AWVALID signal only when it drives valid address. It is allowed that the master can send multiple overlapping read requests to the same slave. You can also instantiate the AXI Data Width Converter core directly in your design (without AXI Interconnect core) along any pathway between a wide AXI master device and a narrower AXI slave. What is APB strobe? APB bridge. AXI3 supports write interleaving. 5 Write data interleaving] "The order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions. November 28, 2019 by Stephen St. This means that in order to complete the transaction, sometimes in the future the matching address cahnnel id is put on the AXI adress channel lines. note: Both the masters are accessing the same slave. Number of Interleaved Memory Controllers: 1 ; AXI Performance Monitor for PL-2-NOC AXI-MM pins: Checked. The AXI4-Lite Cross-bar interconnect is used to connect one or more AXI4-Lite compliant master devices to one or more AXI4-Lite compliant slave devices. Is it possible with single-master cases also?-> Yes. One major up-dation seen in AXI is that, it includes information on the use of default signaling andSupports multiple outstanding transactions: * Supports connected masters with multiple reordering depth (ID threads). pdf". In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. 1) March 7, 2011. Requested operations will be split and aligned according. This feature was retracted by AXI4 protocol. I have seen many IP providers e. >Is it used only when we have multi-master cases? No. Palette data can be RGB or YUV. Enables sharing the AXI CDMA module between multiple request sources, interleaving requests and distributing responses. awaddr { Write address, the write address bus gives the address of the transaction. 1A, the data transmitted by the AXI masters through an NoC router are transferred to an AXI slave 30 through an NI 20. メモリインターリーブ （ 英: memory interleaving ）とは、 主記憶装置 と CPU との間の データ転送 を高速化する方法の一つである。. Sc. Ensure that All Inputs and All Outputs are both unchecked. Write interleaving is hardly used by regular masters but can be used by fabrics that. A. The last piece of the burst 8 transaction (RLAST) is asserted in. Select PS-PL Configuration and expand the HP Slave AXI Interface. Why do we need AXI protocol? The AXI is a point to point interconnect that designed for high performance, high speed microcontroller systems. 0 james_20110801. axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and. By disabling cookies, some features of the site will not workDMA RAM interface demultiplexer module for write operations. Each configured AXI port consists of the signals listed in the following table. Issues B and C of this document included an AXI specification version, v1. "AXI3 supports write interleaving. By disabling cookies, some features of the site will not workIn the waveform window, expand the write data channel of the m00_axi interface. 1 Removal of WID. See the tests directory, verilog-axi, and verilog-axis for complete testbenches using these modules. You say just an out-of-order responses by the interleaving. 0 and v2. 就业和读研问题请走付费咨询，技术细节问题请在评论区讨论。. Though it’s a bit different from Abstraction. although me have twos questions info AXI according hi. Is AXI write data interleaving used when we have multi-master cases?-> Yes. It is part of the Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications. Hold Off Refresh for Read/Write: This allows the controller to delay a refresh to permit operations to complete first. but i have two questions about hi. sv","path":"src/axi_atop_filter. 0/4. By disabling cookies, some features of the site will not workI'm a graduate student living in south Korea. Checks all snoop transactions are ordered. This document gives explanation about Cortex-A9 AXI masters. It connects one DDR4 device and two interleaved LPDDR4 devices, which requires one NoC instance to configure the DDRMC for the DDR4 device and another NoC instance to configure the two interleaved DDRMCs. 1. CPUはコンピュータの動作に必要なデータや命令を 主記憶装置 とやり取りしながら処理します。. Performance constraint on the minimum expected bandwidth for write transfers in a given time interval. 本篇文章给大家讲解 AXI协议的feature和典型应用场景。. Prefix H Denotes Advanced High-performance Bus (AHB) signals. — The read and write acceptance capability of each slave interfaceA company shall be a Subsidiary only for the period during which such control Subject to the provisions of Clauses 2, 3 and 4, ARM hereby grants to LICENSEE a perpetual, non-exclusive, non-transferable, royalty free, worldwide licence to:(i) use and copy the relevant AMBA Specification for the purpose of developing and having developed products. 1. Appendix A Comparison with the AXI4 Write Data Channel Read this for a description of the key differences between the AXI4-Stream interface and the AXI4 write data channel. 4. Besides Cortex-A9 master there are the other masters (DMAC, PL AXI masters) and there are AXI interconnects, that are at the same time slaves and masters, and passes write data from multiple sources (slave. Recently, I read "AMBA AXI Protocol. some will put the single word on a word sized bus and allow unaligned addresses. By the time these commands arrive at our new AXI-lite bus master, they are bundled into 34-bit words as shown in Fig. e. 5k次，点赞20次，收藏158次。Transaction ID信号，使AXI4协议可以完成自身的乱序机制，从AXI3到AXI4的进化中，write interleaving被取消了，大的方向下，AXI遵循着相同ID顺序执行，不同ID乱序执行的原则，同时从主设备-互联网络-从设备的连接中，Transaction ID可能会出现额外的位扩展. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. Double-click the AXI GPIO IP block to customize it. sv","contentType":"file"},{"name":"axi. {"payload":{"allShortcutsEnabled":false,"fileTree":{"src":{"items":[{"name":"axi_atop_filter. PG059-AXI-InTERconnEcT 编辑者： 时 间：2014-12-16 Introduction介绍 Xilinx LogiccoRE IP AXI In. Pass condition: If trace_tag is set to. AHB does not support write strobes while AXI supports it. 3. UVM TestBench to verify Memory Model. " 1. This site uses cookies to store information on your computer. Multiple Intellectual Property (IPs) are integrated in a single SoC and these IPs communicate with the help of various bus protocols. If the slave has interleaving depth of 2, then the slave can receive up to 2 different IDs of write data transactions out of order. Chapter 4 Transfer Interleaving and Ordering Read this for a description of the stream interleaving and ordering restrictions. AXI Data Slave Interface. Support for Read-only and Write-only master devices, resulting in reduced resource utilization. WID signal is not supported in AXI4. In write transactions, in which all the data flows from the master to the slave, the AXI protocol has an additional write response channel to allow the slave to signal to the master the completion of the write transaction. ( int beat_num = -1 ) Returns the total number of bytes transferred in this transaction or beat number. [1] [2] AXI has been introduced in 2003 with the AMBA3 specification. The HBM2 controller asserts the Read data in clock cycle TB. AXI3 supports locked transfers, AXI4 does NOT support locked transfers 4. Secondly, the interconnect must ensure that. int attribute. The very large increase at the end of the functions (highlighted by the red square) indicates a. The problem is with your combination of the write address and the write strobes. but i got two questions about AXI after hi. Simran Sarai 2014. Transaction ID信号，使AXI4协议可以完成自身的乱序机制，从AXI3到AXI4的进化中，write interleaving被取消了，大的方向下，AXI遵循着相同ID顺序执行，不同ID乱序执行的原则，同时从主设备-互联网络-从设备的连接中，Transaction ID可能会出现额外的位扩展. amba 3. 1 PG059 April 5, 2017 89 Chapter 3: Designing with the Core AXI Downsizer The Width Conversion core performs a downsizer function whenever the data width on the SI side is wider than that on the MI side. 主に以下のような用途がある。 誤り検出訂正に使う。。特にデータ転送、ディスク. Architecture AXI protocol is Burst-based transactions with only start address issued. On an AXI bus, IDs indicates the correspondence between addresses and data. Interleaving as a study method means learning more than one subject or skill and switching between them. io and either CPI or AXI for CXL. 1 Answer. It can be used to terminate device-to-device DMA operations with reasonable performance. 1. 2. Since the scoreboard is a uvm_component. pdf". It has been described as shown below. We would like to show you a description here but the site won’t allow us. Supports. For each write or read, start_delay AXI cycles are introduced after each command before the next write or read is issued. AXI4 does NOT support write interlacing. AMBA AXI and ACE Protocol Specification Version E. I have seen many IP providers e. The AMBA AXI4 Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. You will see that wvalid is indeed changing while tready is low which is against the AXI specification. しかし、高速に動作するCPUに. 4 Standards Compliance The DW_axi_gs conforms to the AMBA 3 AXI and AMBA 4 AXI specifications defined in the AMBA AXI and ACE Protocol Specification from ARM. If the transmit replay buffer does not have sufficient place to store the PCIe completions, the PCIESS does not transfer the read transaction. The AXI master writes to memory locations @0x2000000 to 0x3fffffff. Next Section. Read transactions are handled similar to write transactions, except that before transferring the transaction to the AXI4 master read channel, the PCIESS checks the transmit buffer for available space. AXI4 does NOT support writers intersect. We could not find that page in version E or the latest version, so we have taken you to the first page of version E of AMBA AXI Protocol Specification. 2. Write strobes. 标准化：配套提供标准模型和检查器以供设计人员使用。. No. The problem is with your combination of the write address and the write strobes. • AXI Data FIFO connects one AXI memory-mapped ma ster to one AXI memory-mapped 1. Parametrizable interface width and AXI burst length. . 文章浏览阅读2. 是否支持读交织只与slave的设计有关。. The data widths supported are: 32, 64, 128, 256, 512 and 1024. 读交织 ：简单来说，读交织是out of order乱序的其中一种实现形式。. With the new AXI4-Stream protocol (see below), write interleaving is still available. Key Words: NIC 400, AXI, AMBA Designer etc. because this sentence has been described "it is acceptable to interleave the read data of transactions with different ARID fields. 随着 IP 通用用户接口普遍采用 AXI4 标准，AMD 用户将从中受益。. Figure 2-19: AXI Reference Guide UG761 (v13. AXI3 master devices must be configured as if connected to a slave with a Write interleaving depth of one. Enabling the Debug Report x. In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. The Write data interleaving of AXI protocol specification says: "A master interface that is capable of generating write data with only one AWID value generates all write data in the same order in which it issues the addresses. Spring. pcie_axi_dma_desc_mux module . 0 Product Guide for Vivado Design Suite PG059 March 20, 2013 AXI Interconnect Product Guide v2. 1. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol SpecificationLogiCORE IP AXI Interconnect v20 Product Guide for Vivado Design Suite PG059 March 20 2013 AXI Interconnect Product Guide v20 2 PG059 March 20 2013 Table of Contents…Interleaving reading and writing In general, a program performs both input and output and these are interleaved. Enables sharing the PCIe AXI DMA module between multiple request sources, interleaving requests and distributing responses. I was going through write data interleaving section in ARM AXI3 protocol. AXI Verification Plan - Free download as PDF File (. This feature was retracted by AXI4 protocol. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol SpecificationInterleaving is a process or methodology to make a system more efficient, fast and reliable by arranging data in a noncontiguous manner. As a result, AXI4 removed support for write data interleaving, which then removed the need for the WID signal (it was only needed to work out which outstanding write transaction the data related to). This site uses cookies to store information on your computer. All rights. Proprietary Notice This document is NON-CONFIDENTIAL and any use by you is subject to the terms of this notice and the Arm AMBAFree essays, homework help, flashcards, research papers, book reports, term papers, history, science, politicsAXI Interconnect v21 LogiCORE IP Product Guide Vivado Design Suite PG059 April 6 2016 AXI Interconnect Product Guide v21 2 PG059 April 6 2016 Table of Contents…AXI write data interleaving. This example connects many different DDR devices simultaneously in one design to communicate to PS through NoC. Memory analysis. posiible to achieve required through put as before using this sysytem? Any replies will be greatly appreciated. By continuing to use our site, you consent to our cookies. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition Description: Workaround: Status. A locked transaction is changed to a non-locked transaction and propagated by the MI. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering 1. 是否支持乱序只与slave有关，与master无关。. AXI Master Configuration for ACP Access 10. • It has a rich set of configuration parameters to control AXI functionality. AXI4, all write data for a transaction must be provided in consecutive transfers on the write data channel. If a slave does not support write data interleaving (see Write data interleaving on page 8-6), the master must issue the data of write transactions in the same order in which it issues the transaction addresses. Figure 2. AXI BRAM. Write-Write-Write-Write or Write-Read-Write-Read, etc. To maintain uniformity in naming the components/objects, all the component/object name’s are starts with mem_ *. D14Supports AXI Master, AXI Slave, AXI Interconnect; Supports all ARM AMBA AXI 3. erification of a. >In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave? First of all, an AXI4 master must not issue interleaved write data. CS0 CS1 CS2 CS3If multiple real-time axi-streams are interleaved by an AXI Stream Switch at high data-rate (i. Verification takes almost 70 % time in design cycle hence re-usable verification environment of these commonly used protocols is very important. Help me to understand the reasoning behind the following ordering rule imposed by AXI protocol for write data interleaving. 2、什么是interleaving交织机制. Hi I am using Vivado 2017. AXI Interconnect v21 LogiCORE IP Product Guide Vivado Design Suite PG059 April 6 2016 AXI Interconnect Product Guide v21 2 PG059 April 6 2016 Table of Contents…Gaming, Graphics, and VR. I think data interleaving should not be done within a single burst. close to full bandwidth in the interleaved output stream, and maybe also in one of the input-streams, assuming the rest are slow), then we need to FIFO-buffer data corresponding to at least the size of one arbitration-block on each of the switch. 1. Synopsys NO supporting write interlock in AXI3. "For a slave that supports write data interleaving, the order that it receives the first data item of eachHowever, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. In includes the following features: The address widths can go upto 64-bits. Upload File; Most Popular; Art & Photos; Automotive; Business; Career; Design; Education; Hi-TechJoins a read and a write slave into one single read / write master. AXI3 supports locked transfers, AXI4 does NOT support locked transfers 4. SIMON FRASER UNIVERSITY. When 256 bits data is chosen in the GUI, this bus should be left undriven. B. AXI Protocol The AXI protocol: Permits the address information to be transferred ahead of actual transfer. . This doesn't cover the case of simultaneous Read and Write commands, which is certainly possible for AXI. The write data channel, which carries write data. All five transaction channels use the same VALID/READY handshake processInterleaving allows you to send WID transfers for a number of outstanding AW transfers, BUT. This approach makes good use of memory. The reason interleaving was in AXI3 was to maximise the write data bus bandwidth, using gaps in master's write data availability to pass transfers for other write transactions. There are a lot more interpretations of a BFM, BFMs typically reduce the job of a testbench by making it more data focused. Get a descriptor for transaction. The Advanced eXtensible Interface (AXI), part of the ARM Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications, is a parallel high-performance, synchronous, high-frequency, multi-master, multi-slave communication interface, mainly designed for on-chip communication. The base addresses for slaves in the interconnect are also hence assigned in multiples of 4K. Provides test pattern generator as replacement to one of the 2 rendering sources on stream1. 1) A1 A2 B1 B2 (In-order)-> This is legal. The AMBA AXI protocol supports high-performance, high-frequency system designs. 16. The problem I am facing is in AXI interface of MIG where 4-bit ID signal is present for all the transacti AXI-4 questions. The write data interleaving depth is the number of addresses for which a slave can accept interleaved data. #- Check that the Interconnect is forwarding the correct write data with respect to address issued. Customize the AXI GPIO IP block:. 4 Normal write ordering. dfblob:120001dbc4d dfblob:c39f478f34a. transfer. The pcie_us_axis_cq_demux module can be. As shown in FIG. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. svt_axi_system_transaction:: slave_port_id [$] port_id of the slave transaction (s) corresponding to the master transaction. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are. Scenario 1: There is Only 1 AXI master (with support of only 1 Master ID) doing transaction to a slave which is capable of handling multiple outstanding addresses. 1A, the data transmitted by the AXI masters through an NoC router are transferred to an AXI slave 30 through an NI 20. Slave write transactions support incrementing address bursts, fixed bursts, wrapping bursts, and narrow type transfers. With interleaving, students learn by tackling a mix of related concepts, forcing the brain to work hard to recall prior learning and determine which strategies or skills to use to solve them. Supports all burst types. FIG. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed. emory. In AXI Interconnect IP configuration, I changed the Acceptance parameter to 5 from 1 (All sides : Master Read/Write, Slave Read/Write). By continuing to use our site, you consent to our cookies. But the first item of write data must be issued in the same order as the write address. <二. Synopsys supporting burst lengths up to 256 beats in AXI3 I have also seen many IP providers e. [AXI spec - Chapter 8. All five transaction channels use the same VALID/READY handshake process Interleaving allows you to send WID transfers for a number of outstanding AW transfers, BUT. Recently, I read "AMBA AXI Protocol. svt_axi_slave_read_data_fixed_interleave_block_sequence; svt_axi_slave_response_sequence; svt_axi_slave_tlm_response_sequence; svt_axi_slave_random_snoop_sequenceAXI Slave Write Transactions. In practice, removing write interleaving from this part of the AMBA standard makes certain aspects of the AXI protocol easier to handle. Thank you. Figure 1. By continuing to use our site. allavi. Table 2-2 Write address channel signals. I'm studying nearly AMBA 3. 3. Resources Developer Site; Xilinx Wiki; Xilinx GithubThis book is for AMBA AXI Protocol Specification. • Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization.